Alibaba Launches Campaign to Conquer the AI Central Chip Hub

The agent boom driven by OpenClaw’s “Lobster” since the beginning of the year needs no elaboration, and the potential semiconductor demand it has created has already elevated many sellers to stardom.

On March 24, Alibaba DAMO Academy unveiled its key chip products—the new flagship CPU Xuantie C950 and high-efficiency CPU Xuantie C925. Their direction is very clear—targeting the hardware needs of AI agents that are expected to explode this year.

Industry insiders believe that, measured by parameters like clock speed, this is the first time an open-source RISC-V architecture CPU’s single-core performance has truly entered the high-end ARM / early x86 generation range, reaching the single-thread performance level of truly commercial server CPUs.

In the past, RISC-V was mostly perceived as low-end, marginal, and lightweight. But after the Agentic AI era, changes are happening.

Previously, AI bottlenecks were concentrated in GPU computing power, but in the Agentic AI stage, bottlenecks are spreading to memory, I/O, and system scheduling. The computing paradigm is shifting from a single GPU to a heterogeneous architecture.

Unlike traditional compute chips that pursue FLOPS, this type of RISC-V CPU no longer emphasizes faster computation but is responsible for organizing dispersed computing power, becoming the central hub of AI system operation.

Lu Da, Chairman of the RISC-V International Foundation Board, told Wall Street Insights, “There is a huge demand in the market right now—people want to see major international companies adopting RISC-V as their main product.”

For Alibaba DAMO Academy, years of dormant preparation have finally led to the moment of monetization with great potential.

Breaking into High-End

In the AI agent era, Alibaba aims to define high-end CPUs under new demands.

On March 24, DAMO Academy announced the new flagship CPU Xuantie C950. It adopts the open-source RISC-V architecture. Additionally, leveraging RISC-V’s open-source features, it is equipped with self-developed AI acceleration engines and natively supports large models like Qwen3 and DeepSeekV3 with hundreds of billions of parameters.

Unlike traditional closed-source architectures, RISC-V’s open, flexible, and customizable nature is widely regarded as a “born for AI” emerging architecture, which could reshape the existing chip industry landscape.

This time, RISC-V has truly moved a step toward high-end computing.

For example, Xuantie C950 broke through 70 points in the SPECint2006 benchmark for the first time, with single-core performance exceeding 22/GHz, reaching a maximum frequency of 3.2GHz, and smoothly running large models with hundreds of billions of parameters for the first time.

This directly sheds the low-end label from RISC-V, stepping into the most core tracks of high-performance computing and AI computing.

Industry experts believe that once RISC-V can establish a foothold in high-performance and AI scenarios, it will no longer be just a cheap, flexible alternative but will begin to influence the division of labor in the entire chip ecosystem and compete directly with architectures like x86 and ARM.

What’s most noteworthy about the C950 is not just its performance but its “usability.” Many chip promotions focus on extreme performance, but what truly determines whether a product can be scaled is often not a single benchmark score but whether it can run stable under real workloads.

DAMO Academy conducted joint testing with server workloads such as MySQL, Redis, Nginx, and OpenSSL. Results show that after software and hardware co-optimization, C950’s performance has reached the industry’s top tier, with cloud network and storage performance improving by over 30% compared to some mainstream products.

This means C950 is not just for labs but is trying to enter more realistic cloud computing, generative AI, high-end computing, and edge computing scenarios.

Moreover, supporting all features of RVA23.1 and optional extensions indicates that its software ecosystem, system compatibility, and platform adaptation are already approaching server-grade, automotive-grade, and AI-grade platforms.

For RISC-V, this standardization capability is crucial because it determines whether this architecture can truly enter mainstream operating systems and industrial chains.

Alibaba DAMO Academy’s Chief Scientist Meng Jianyi openly stated that although RISC-V has penetrated fields like smart terminals, automobiles, home appliances, and communications, long-term issues such as performance limitations and software ecosystem barriers remain. Only by launching high-performance benchmark products can RISC-V seize opportunities in the AI era, compete with traditional architectures, and open up application markets.

This is why the new flagship CPU Xuantie C950 launched by DAMO Academy today is so highly regarded by the market.

Years of Dormancy

Initially, the market mostly viewed AI compute power as the domain of GPUs, but the Agentic AI era is different.

When systems are not operated by a single person but by countless intelligent agents running simultaneously, token calls, KV-Cache loads, initial token latency, task serial and parallel switching all elevate the importance of CPUs.

Meng Jianyi emphasized that since model capabilities have crossed certain thresholds, a large number of AI-interactive tasks will emerge in the future. This leads to a need for CPU architectures to undergo new changes, requiring re-design for the AI era.

Now, CPUs are no longer just supporting roles next to GPUs but are central to system task scheduling and data flow.

DAMO Academy is working in this direction. They released two native RISC-V AI computing engines: a 4K ultra-wide Vector engine and a Matrix engine, both unified with CPU addressing, aiming to eliminate data copy bottlenecks and integrate general computing with AI compute natively.

More importantly, these engines can now run top-tier open-source models like Qwen3 and the resource-intensive DeepSeekV3 in full capacity: Qwen3 outputs 34 tokens/sec with an initial delay of 3.4 seconds; DeepSeekV3 outputs 18 tokens/sec with an initial delay of 1.7 seconds.

This marks the first native support of RISC-V CPU for large models with hundreds of billions of parameters. It signifies a shift in architecture positioning: RISC-V is moving from general-purpose CPU to a new compute hub for the AI agent era.

Meng Jianyi revealed that they are already working on inference tasks, with models of various sizes from Qianwen, and each first-round model is being adapted to Xuantie CPUs first.

In fact, Alibaba has not just started working on RISC-V today.

Since 2018, Alibaba has been among the earliest teams domestically to deploy RISC-V. The Xuantie C910 released in 2019 was one of the most powerful RISC-V CPUs in the industry at the time, breaking 2GHz and pushing SPECint2k6 to 7/GHz.

Back then, the market already recognized that RISC-V has no inherent performance ceiling. Later, C910 also saw real-world deployment.

Huang Shaorui, General Manager of Allwinner Technology’s Product R&D Center, recalled to Wall Street Insights that they began applying RISC-V in products as early as 2019. Initially, software was very immature and painful, but as the ecosystem developed, supporting tools and deployment became almost effortless.

By 2024, DAMO Academy and the Institute of Software at the Chinese Academy of Sciences produced the world’s first stable RISC-V laptop; European cloud provider Scaleway launched the first RISC-V cloud instance globally, all based on C910. Moving forward, the Xuantie C930 released in 2025 will cross the entry threshold for server chips.

Looking back, Alibaba’s Xuantie efforts are clear: not chasing trends but pushing RISC-V towards high performance, commercial viability, and server-level capabilities generation by generation.

Meng Jianyi admitted that transforming standards into IP and achieving mass production takes a long cycle. Facing practical bottlenecks, leading companies must endure solitude and make long-term, substantial investments, focusing on the ecosystem’s value over the next five or even ten years.

Ecosystem Play

The true moat is not just the CPU itself but the combined architecture, ecosystem, standards, and industry collaboration. This time, Alibaba is building a comprehensive open ecosystem around RISC-V.

DAMO Academy released the Flex platform, packaging processor modeling, development environment, and software toolchains into a complete capability, allowing customers to use high-performance Xuantie CPUs as a base while enabling deep customization.

Last year, Xuantie supported 35 clients with 38 CPU low-level modifications, over half of which focused on AI acceleration, storage optimization, and reliability enhancement. This shows Alibaba is not just selling IP but platformizing chip-making capabilities.

Regarding customization potentially causing fragmentation, Lu Dai believes RISC-V’s greatest advantage is its flexibility for tailored design. Many official standards are extensions evolved from autonomous exploration, so standardization does not hinder innovation but enables continuous iteration within an open system.

Meng Jianyi echoed this, stating that ecosystem requirements for underlying OS adherence to standards, while leaving room for innovation above, are key to RISC-V’s sustained vitality and self-consistency.

For industry clients, this effectively lowers the barrier to high-end custom chips; for the RISC-V ecosystem, it shifts from an open-source idealism to a practical industry deployment path.

Huang Shaorui mentioned that as demand for general compute power in products like intelligent robots grows—such as deploying models like Lobster—Allwinner chose Xuantie because of its long-term sustained investment and high compatibility with terminal SoC product matrices.

Jiang Tao, Vice President of Resources Development at Nanjing Chipsee, cited complex power supply chips as an example, noting that without DAMO’s open-source ecosystem kernel support, traditional power companies would struggle to meet the digitalization challenges brought by surging compute power. Although RISC-V is still like a “youth” needing support, its cost competitiveness and modular flexibility make it a powerful tool for enterprises to develop high-end product lines and leapfrog competitors.

Meanwhile, Alibaba Xuantie is deeply involved in the RISC-V International Foundation, leading the development of server-grade chip standards, participating in key specifications like BRS and RPMI, and promoting community discussions on Matrix extensions.

As Meng Jianyi said, they have abandoned the pitfalls of traditional NPUs’ ecosystem formation, choosing instead to build AI acceleration engines based on standards like RVV within the RISC-V ecosystem, laying a foundation for long-term ecosystem prosperity.

This is no longer just product competition but a contest for ecosystem discourse rights.

The following is an interview transcript with Alibaba DAMO Academy Chief Scientist Meng Jianyi, RISC-V International Foundation Chairman Lu Dai, ChipWing Information Technology CEO Xiao Jianhong, Nanjing Chipsee Resources Development Vice President Jiang Tao, and Allwinner Technology Product R&D Center General Manager Huang Shaorui:

All-Weather Tech: What are the current practical bottlenecks in RISC-V development?

Meng Jianyi: The main bottleneck is time. Because transforming a RISC-V standard into IP, then into chips, and scaling those chips, takes a cycle like this. We held the fourth Xuantie Ecosystem Conference in Shanghai, and the last one was four years ago. In four years, their annual RISC-V output will reach 100 million units, and with about a hundred such companies, the community foundation will be solid. So, the key is time—about four years. We started collaborating at that time.

All-Weather Tech: GTC just wrapped up, and it’s clear that the demand for compute power in the era of large models is changing dramatically. They also launched CPUs targeting data centers. How will we respond to these refined demands?

Meng Jianyi: This year will be a big year for inference, and models have already crossed certain thresholds. They will be used more deeply, turning into productivity tools—Agentic AI. We need to handle massive AI interactions, such as querying databases, searching online, storing data, and so on. These bottlenecks were discussed by Jensen Huang.

Today, he believes new CPUs should be designed for AI, like his Vera, which features strong compute capabilities, security, and excellent I/O. He redefined CPU architecture, combining two sockets into a large chip.

Overall, CPU architectures are evolving, and I think in the AI era, CPUs need to be redesigned. The second aspect is compute power for AI, which is already underway.

All-Weather Tech: What are your current deployments?

Meng Jianyi: Our Xuantie C950 is optimized for this direction. It offers high performance, excellent access, and security—these are aligned with this goal.

All-Weather Tech: We are now in the transitional phase of physical AI. RISC-V chips have deep roots in IoT. In the era of physical AI, what opportunities do RISC-V chips have compared to others?

Huang Shaorui: Allwinner mainly focuses on terminal and edge products. Since around 2019, we’ve been applying RISC-V in products. Over these years, we see rapid development—initially very painful due to immature software, but ecosystem growth has made supporting tools and deployment almost effortless now.

For new products, we need low-cost software, and the foundation is well established. For terminal applications, like robots, we add small AI modules on top of general-purpose CPUs; for general compute needs, demand is slowly expanding—deploying Lobster models, for example, now requires 4-core or 8-core chips, which indicates large-scale RISC-V deployment in the future.

Meng Jianyi: Physical AI is a more distant concept, even more challenging than Agentic AI, because it involves interaction with the physical world. Chips for Physical AI are mostly single-chip solutions with high energy efficiency. RISC-V is exploring this path. Previously, data centers relied on many GPUs or large clusters; Physical AI demands even higher compute efficiency. Our opportunity lies in adapting to the rapid evolution of Physical AI models with more advanced or open architectures.

All-Weather Tech: Which major clients are experimenting with RISC-V chips?

Lu Dai: We hope large companies adopt RISC-V as a main product. In China, Alibaba does well, and many domestic RISC-V companies exist. But a big difference is that international giants are also developing RISC-V products as main offerings.

All-Weather Tech: Is Xuantie being used for inference and training of the Qianwen models?

Meng Jianyi: Training is not yet done; inference is ongoing. Many models are using Qianwen, which has various sizes. Qianwen joins our “Wu Jian” alliance, and their first models are adapted to Xuantie CPUs first.

All-Weather Tech: Does Shanghai have advantages in open-source community ecosystems?

Xiao Jianhong: China’s semiconductor industry has developed rapidly over the past five and a half years. Our papers at top international conferences used to be rare; now, about a third come from China. Shanghai hosts many excellent companies with R&D distributed across the city, not just headquarters.

Regarding open-source, I decided in 2020 to adopt RISC-V early on. We were among the first to use Xuantie, driven by the need for reliable, high-performance, and scalable solutions for applications like 5G, IoT, satellite communications, and more. RISC-V’s rapid extensibility and evolving ecosystem have allowed us to go from initial ideas to nearly 100 million shipments, with products sold globally, including Europe and the US.

The ecosystem supports AI deployment, especially continuous connectivity—satellites, cellular networks, and more. For example, autonomous vehicles require constant connection; losing control is dangerous. So, satellite and cellular are critical.

AI is increasingly cloud-based, but edge AI remains vital, especially for low-power models, medium-scale compute, and future devices like AR glasses that need large models. Combining compute, connectivity, and AI processing is essential.

Physical AI involves industry-specific deployment—like replacing steam with electricity in various sectors—requiring deep customization, sensors, security, and integration. Our goal is to enable industry-specific physical AI, which depends on open ecosystems and collaboration.

We are working with top industry players and DAMO Academy. RISC-V’s advantages are evident in international competition and industry deployment. We see huge potential in satellite communications, CPU+NPU integrations, and exploring new AI acceleration avenues.

All-Weather Tech: How will manufacturing of CPU+NPU or AI accelerators be arranged?

Jiang Tao: I’m from Nanjing Chipsee, which makes high-power power supplies. Power supplies are now very different—larger compute power demands mean higher management requirements. Our previous power management chips were mostly analog; now, digital power chips are complex, with many digital circuits integrated.

Without DAMO’s open-source ecosystem kernel support, we couldn’t do this. The digital power chips now are large, with many digital components—seven or eight years ago, they were tiny; now, they’re much bigger.

We’re investing heavily in server and automotive power supplies, with shipments exceeding 100,000 units, including high-end power packs for domestic batteries and components for large domestic aircraft. We also collaborate with leading domestic compute companies, developing more complex power management solutions.

Meng Jianyi: If we reach 10 billion chips, with about 100 companies involved, that’s very feasible.

Regarding AI and NPU deployment, we know that NPUs were used earlier in many edge chips. But this approach faces challenges—ecosystem formation is difficult, as NPUs are maintained and upgraded by a single company. Our new AI acceleration engines, built within the RISC-V ecosystem, are different. For example, our RVV standard allows programs to run on the core, enabling an AI ecosystem that traditional NPUs can’t support.

We’re also developing the Matrix standard, which is already released. As standards mature, we can transition to them.

In short, for NPU development, we’re building on RISC-V’s standardized interfaces. With continuous iteration, our NPUs will improve over generations.

All-Weather Tech: Is the industry’s head effect quite prominent in RISC-V?

Meng Jianyi: RISC-V at this stage requires investment. DAMO Academy has spent four years building a large customer base. But that involved huge R&D investments. For smaller companies, immediate survival is a challenge.

For Alibaba, we see the next 5 to 10 years of RISC-V ecosystem value. Our entire layout involves helping others develop, customizing, and launching new products—this is ongoing. It requires patience and perseverance. Both domestically and globally, such companies need to invest heavily, and DAMO is doing just that. The head effect is very important.

All-Weather Tech: The new chip already achieves a balance of generality and customization—what conditions made this possible?

Meng Jianyi: When we launched C950, we emphasized general performance, measured by SPECint. But RISC-V is more than that. We’re pushing extensions and exploring performance limits.

For example, besides SPECint, we added benchmarks relevant to cloud computing, databases, and other typical scenarios. We’ve reached top-tier levels in the industry. We also added instruction set extensions for storage and networking, improving performance by another 30%. These are part of customization. These instructions are still being promoted and standardized, and may become future general-purpose features.

In summary, DAMO has demonstrated that RISC-V can produce specialized products that outperform general-purpose ones in certain markets. We aim to give this capability to others so they can develop more competitive products. This is how RISC-V differs from previous approaches—through real actions.

Jiang Tao: Regarding power supplies, the current situation is that we’re among many participants. Besides consumer products like smartphones, we also supply complex power management chips for vehicles and servers. Our digital power chips now are very complex, with multiple LDOs and DC-DC circuits—16 or 32 channels.

We also develop high-power solutions like vehicle charging chips, which are multi-channel and require support for RISC-V cores. Without RISC-V open-source support, we couldn’t do this efficiently.

Our chips are used in high-end power packs, domestic aircraft, and for leading domestic compute companies. The demand for complex power management is growing, and RISC-V’s modularity and cost advantages are helping us develop high-end products and leapfrog competitors.

All-Weather Tech: How to balance fragmentation and standardization?

Lu Dai: RISC-V’s biggest advantage is its flexibility. It’s a standard but allows very flexible customization. Companies can choose different extension paths based on needs.

The RISC-V architecture divides into “mandatory extensions” and “optional extensions.” Optional extensions are not yet officially approved; companies can develop their own “custom extensions.” Whether these become standards depends on market adoption. If widely used and valued, they may be standardized.

Some worry that standardization might reduce innovation, but actually, RISC-V’s standards evolve from customization. Industry consensus can lead to official standards, while ongoing innovation continues in areas without consensus. For example, our Matrix extension has multiple routes, and market acceptance will decide which is best.

Therefore, standardization does not hinder innovation; it enables continuous iteration within an open system. RISC-V’s ability to evolve through market validation is unique.

Meng Jianyi: Standards are not static; they evolve through market verification, absorbing solutions that are industry-accepted into the mainline. RISC-V will become stronger through this dynamic process, which itself is an innovation.

Another innovation is that RISC-V requires adherence to core standards but leaves room for companies to innovate beyond them. The key is to refine the IP for the standard part—making OS support smooth, software libraries stable—and then open up space for users to innovate without rewriting entire kernels, which is costly and risks losing ecosystem support.

The true path is that the ecosystem’s required parts follow standards, while the innovative parts are left open, allowing new industry consensus to form and systems to evolve again. This cycle creates a continuous, coherent, and vibrant innovation system. I see this as a unified, open innovation process.

All-Weather Tech: Why did Allwinner choose Xuantie as a partner?

Huang Shaorui: The main reason is our recognition of Xuantie’s sustained long-term investment in RISC-V. For terminal SoC products, we need reliable, high-performance, scalable solutions. Xuantie’s team has been committed and consistent.

Second, Allwinner’s product portfolio is diverse. Since 2019, we’ve been applying RISC-V across many products. Ecosystem growth has been rapid—initially painful due to immature software, but now tools and deployment are almost effortless.

We’ve supported RISC-V in robots, edge devices, and other applications, enabling us to develop new products with low-cost software and high customization. The combination of IP capabilities and ecosystem support allows us to quickly implement solutions for various scenarios.

What are the main benefits of choosing Xuantie?

Huang Shaorui: Our product lines include six series, two of which mainly use RISC-V IP. Using Xuantie IP, we can meet specific needs, collaborate closely, and integrate into our solutions. This also reflects in the architecture and delivery capabilities of the IP.

Jiang Tao: We chose RISC-V because it offers a chance for a new company like Nanjing Chipsee to leapfrog competitors. RISC-V is still like a “youth,” and needs industry and developer support to grow. Our partnership with DAMO Academy is based on their investment, leadership, and proximity.

This decision has helped us expand customers and shipments, proving our choice was correct. The benefits include lower costs, high flexibility, and high added value through customization.

All-Weather Tech: Is the launch of this new chip strongly related to OpenClaw?

Meng Jianyi: The AI wave is fair to everyone. Our two products are aimed at this trend, but not solely for Lobster. The phenomenon of Lobster may evolve into other forms, like Rhinoceros, or change again.

We firmly believe Agentic AI will advance, which requires stronger CPUs, better CPU-GPU coordination, and system optimization. The future will see a rethinking of how AI workloads are handled.

The trend is shifting back from GPU-centric to more balanced general compute, because real-world interactions demand versatile, general-purpose computing alongside specialized acceleration.

Having good AI support is essential, but general compute remains vital. The bottleneck in general compute will be addressed by how everyone chooses to develop.

This is not just a Lobster phenomenon but a fundamental direction. If you have excellent AI support, you can produce high-quality work efficiently—like writing articles in advance—that’s very appealing.

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